Failure analysis is the study and presentation of observable or measurable phenomena. Risk assessment, on the other hand, is when root causes are studied to predict the potential for future failures. In this article, the author describes a structured problem-solving approach that consists of failure analysis, risk assessment, and advanced modeling. A case study is also presented in which the probability of future failures, due to a delamination defect, is determined based on field returns.

Modified Talbot X-ray interferometry provides three contrast modes simultaneously: absorption, phase, and dark field/scattering. This article describes the powerful new imaging technique and shows how it is used to characterize various types of defects in advanced semiconductor packages.

In this article, the authors evaluate micro CNC milling as an alternative to manual parallel lapping for mechanical cross-sectioning of flip-chip packaged samples. They describe both processes, and how they compare to other cross-sectioning techniques, and clearly illustrate the differences. SEM images of a manually polished sample show process-induced cracking, chipping, and delamination at the die-C4 interface. In contrast, the CNC-milled sample is artifact-free and the C4 bumps are uniformly exposed along the entire length of the cross-section.

This article reviews the basic principles of scanning acoustic microscopy (SAM) and presents several case studies demonstrating its use in failure analysis and counterfeit detection. The FA case studies show how SAM is used to detect delamination, cracking, and manufacturing defects in ceramic chip capacitors and resistors, voids in a full-bridge rectifier, and a radiation-induced defect in a microprocessor. In cases involving counterfeit ICs, CSAM images reveal the presence of an abnormality on component packages, evidence of relabeling, and popcorn fractures indicative of the use of excessive heat and force to dislodge components from circuit board assemblies.

This article presents a case study of an IC failure that occurred in a downhole drilling environment. It describes the tests and examinations that were performed and explains how investigators determined that the Kirkendall effect contributed to the failure.

With the July 2006 implementation of RoHS (the restriction of the use of certain hazardous substances in electrical and electronic equipment), the electronics reliability industry has seen a changeover to lead-free solders and “green” mold compounds that have no bromine- or antimony-based flame retardants. This article addresses some of the challenges caused by implementation of the new requirements.

This article assesses the capabilities of failure analysis techniques in the context of 65 nm CMOS ICs. It demonstrates the use of OBIRCH, voltage contrast, Seebeck effect imaging, SEM and TEM techniques, and FIB cross-sectioning on failures such as dielectric breakdown, open and resistive vias, voids, shorts, delaminations, and gate oxide defects.

This article presents a new technique for monitoring the health of lithium-ion cells. Whereas traditional methods use current, voltage, and temperature data to infer the overall health of the cell, the new method uses ultrasonic measurements to assess structural changes such as swelling, expansion, ruffling, and delamination. The article explains how and why these changes occur, how they are measured, and how they correlate with loss of battery capacity, safety, and failure. It also discusses the effect of charge and discharge cycles and the factors that contribute to gas generation.

This article provides an overview of the types of failures that tend to occur in photovoltaic (PV) modules in the field and the methods typically used to investigate them. It covers the causes and effects of broken and corroded interconnects, cracked and damaged cells, short and open bypass diodes, delamination, moisture ingress, and encapsulant discoloration. It describes tools and techniques commonly employed in the analysis of PV failures, including IV measurements, electroluminescence, infrared imaging, and visual inspection. It also discusses current and emerging challenges in PV failure analysis and reliability.

Scanning acoustic tomography (SAT) is widely used to detect defects such as voids and delamination in electronic devices. In this article, the authors explain how they improved the spatial resolution and detection sensitivity of SAT by switching from a conventional piezoelectric probe to a capacitive micromachined ultrasound transducer (CMUT) and by using pulse compression signal processing. They also present examples showing how the improvement makes it possible to detect very small defects in multilayer stacks and BGA packages whether in through-transmission or reflection imaging mode.

This article describes two accelerated reliability tests that can help shorten product development cycles for power semiconductor packages. One test simulates the effects of temperature cycling by applying a series of thermal shocks to the test sample. The other test assesses the bond between metals and molding compounds as a measure of thermal cycle resistance. A button shear test is used to measure changes in adhesion strength as a function of time and temperature.

This article assesses the progress that has been made in the development and implementation of through-silicon via (TSV) technology, the work yet to be done, and the challenges associated with potential failure mechanisms.

Plasma focused ion beam (PFIB) systems can generate ion beams with much higher current and are therefore able to remove larger volumes of material at much faster rates while still maintaining precise control of the beam and its milling action. This article explains how the improved performance of PFIB is leading to new applications in delayering, deprocessing, and site-specific failure analysis.

倒装芯片安装设备很难调试使用g conventional FIB tools because their internal circuitry is not easily accessible. New flip chip focused ion beam (FC FIB) systems overcome this limitation, however, making it possible to access circuits from the backside through the bulk silicon. In this article, the authors explain how they used the new system to gain access to signal lines for backside waveform acquisition. They also describe some of the procedures they developed to repair and modify flip chip circuits from the backside and prepare cross-section samples from the backside for failure analysis and characterization.

Although plastic-encapsulated packaging dominates most of the IC industry, deprocessing and reliability testing continue to be a problem, particularly in industries making the switch from hermetically sealed ceramic packages. This article discusses the challenges designers and failure analysts face in the military and aerospace electronics industry stemming from the use of plastic packages. It provides examples of the types of failures encountered and describes the procedures used to detect and identify them.

Reflecting back on the past 45 years in semiconductor failure analysis, the columnist notes that the trend lines have deviated little over that time. He then goes on to point out the relatively few discontinuities, the latest of which, the emergence of the “invisible defect,” takes him back to the beginning of his journey.

A guest columnist shares some of the lessons learned in the course of his career. The wisdom contained in these lessons can be summed up as follows: look at the problem from different perspectives, believe the data, and don’t give up too soon.

The third extended European Failure Analysis Network (EUFANET) workshop, “Smart FA for New Materials in Electronic Devices,” was held in Dresden, Germany, September 17-18, 2012. This article provides a summary of the event with highlights from presentations on flexible organic electronics, crystal defects in SiC, nanoprobing, and the capabilities of nano X-ray tomography.

Engineers at the Fraunhofer Institute for Microstructure of Materials and Systems built and are testing a scanning acoustic microscope (SAM) that operates at frequencies of up to 2 GHz. Here they describe the design of their GHz-SAM and present examples showing how it is used to detect stress induced voids, inspect wire bond interfaces, and examine through-silicon vias (TSVs) in the time-resolved mode.

Electronic components and assemblies are subjected to temperature variations at every stage of life, resulting in the buildup of internal stress. This article explains how such stress contributes to failures and introduces a measurement technique that allows users to visualize stress distributions and assess their effects on lifetime and reliability. Application examples illustrating the capabilities of the new topography and deformation measurement approach are also presented.