Nanoprobing of transistors and resistors is increasing in importance for both design debug and electrical fault isolation. It is thus necessary to understand the impact of scanning a resistor or transistor with an electron beam in order to draw valid conclusions from nanoprobe measurements. In this article, the authors show that exposing samples to electron beams with energies above 4 keV can change the value of diffusion resistors by as much as 30% and that changes can occur at even lower voltages in areas of the sample covered with less material. The article also sheds light on why the changes occur.

Stress voiding is an insidious IC failure mechanism that can be difficult to identify and arrest. It is of particular concern to those who produce and test ICs with aluminum-alloy interconnects or who assess the reliability of legacy devices with long service life. This article explains how stress voids form and grow and how to determine the root cause by amassing physical evidence and ruling out other failure mechanisms. The key to differentiating stress voiding from other types of failures is recognizing that is the result of three distinct physical phenomena, stress, nucleation, and diffusion, all of which must be confirmed before attempting to make process corrections.

这是一个由两部分组成的系列文章的第二篇文章the causes of stress voiding and the evidence required to tie it to an IC interconnect failure. The first part, published in the November 1999 issue of EDFA, focuses on the causes and distinguishing characteristics of stress void failures. Here, that information is applied in the analysis of an actual case of stress voiding. The author explains how he developed evidence of stress, nucleation, and diffusion, the three phenomena required to differentiate stress voiding from other failure mechanisms, and how this evidence pointed to specific processing errors and suggested how to fix them. Although the investigation relied heavily on traditional observational tools, they were applied in new ways using a relatively new technique, FIB backside thinning, to gain critical proof of nucleation and confirm suspected processing errors.

STEM-EBIC imaging, a nano-characterization technique, has been used in the study of electrically active defects, minority carrier diffusion length, surface recombination velocity, and inhomogeneities in Si pn junctions. In this article, the authors explain how they developed and built a STEM-EBIC system, which they then used to determine the junction location of an InGaN quantum well LED. They also developed a novel FIB-based sample preparation method and a custom sample holder, facilitating the simultaneous collection of Z-contrast, EBIC, and energy dispersive spectroscopy images. The relative position of the pn junction with respect to the quantum well was found to be 19 ± 3 nm from the center of well.

This article presents two case histories that shed light on the role of gold in lead-free solder joint failures and the damage mechanisms involved. One of the failures, a brittle fracture of the solder joint, is attributed to the synergistic effects of voids, intermetallic compounds, and CTE mismatch. The investigation of the other failure revealed evidence of tin-whisker formation. As the author explains, the growth of tin whiskers is due to compressive stress in the tin solder material caused by diffusion of end-cap metals (Ni and Cu) and the formation of Sn-Ni-Au intermetallics. In both cases, the failures can be prevented by limiting the thickness of gold on all components.

Off-axis electron holography is a TEM-based imaging technique that reveals dopant anomalies and junction profiles in semiconductor devices. This article explains how the method works and how it is being used to visualize transistor source-drain regions, diffusion-related defects, and other features of interest in TEM samples. It also discusses related challenges and compares off-axis electron holography with other profiling techniques, particularly junction staining.

Lightly doped source-drain diffusions are difficult if not impossible to delineate using wet chemical etching, but with a few process modifications and the use of edge shorting, a 20:1 HNO 3 /HF etch for 5 s at room temperature can reveal almost any junction profile in a CMOS device. The relatively simple process is outlined in this installment of Master FA Technique, which also includes a series of images showing how well the method works.

Latchup has long been a concern for CMOS technologies and is becoming more of an issue with the reduction of transistor dimensions and spacing. Although many techniques for avoiding the risk of latchup have been developed, they generally apply to specific technologies and are not portable to others. In light of the problem, IBM engineers conducted an in-depth evaluation of the structures most sensitive to latchup ignition and the many possible triggering mechanisms. In this article, they describe the work they performed along with the findings and provide practical guidelines on how to minimize latchup regardless of the IC technology involved.

Long-term stability studies indicate that cathode degradation is one of the main failure mechanisms in anode-supported SOFCs. In order to better understand the microstructural degradation mechanisms of the cathode and the influence of oxygen partial pressure at relevant operating temperatures, the authors of this article acquired TEM samples from technological cells to study cation interdiffusion mechanisms and LSM-YSZ interactions, particularly in areas where LSM grains are in contact with YSZ electrolyte. Here they present and interpret the results.

This article reviews recent work aimed at characterizing soft-error effects in SRAM circuits fabricated with bulk silicon FinFETs. Accelerated tests were conducted on 6T planar and FinFET-based SRAM cells by exposing them to high-energy neutrons and alpha particles. Based on test results and simulations, the authors show that soft-error rates are much lower in FinFET devices because the geometry of the fins limits charge collection.

激光探测电压(LVP),一个想法technique, facilitates through-silicon signal waveform acquisition and high frequency timing measurements from active p-n junctions on CMOS ICs. The ICs can be in flip-chip as well as wire-bond packages with backside access to the IC. As the article explains, LVP significantly improves silicon debug and failure analysis throughput time compared to electron-beam probing because it eliminates the need for backside trenching and probe-hole generating operations.

Tin whiskers are single-crystal filaments that can grow from tin-plated copper or nickel components. This article discusses the effect of plating thickness, composition, and grain size on tin whisker formation and explains how to assess damage potential based on microanalysis, whisker length distribution models, and metal vapor arc risk factors. The authors also present and analyze several examples of failures caused by tin whisker formation in space systems.

This article discusses the basic principles of dark current spectroscopy (DCS), a measurement technique that can detect and identify low levels of metal contaminants in CMOS image sensors. An example is given in which DCS is used to determine the concentration of tungsten and gold contaminants in an image sensor and estimate the dark current generated by a single atom of each metal.

This article discusses the advantages of SEM-based nanoprobing and the various ways it can be used to locate defects associated with IC failures. It describes the basic measurement physics of electron beam induced current, absorbed electron, and voltage distribution contrast imaging and presents examples showing how the different methods are used to isolate low- and high-resistance sites, shorts, and opens as well as ion implantation and metal patterning defects.

This article presents a case study of an IC failure that occurred in a downhole drilling environment. It describes the tests and examinations that were performed and explains how investigators determined that the Kirkendall effect contributed to the failure.

This article discusses the challenges involved in testing analog and mixed-signal ICs and provides practical guidance and insights on how to deal with them.

Microelectronics failure analysis is based on several approaches to study and understand the origin of failure. In addition to “classic” elemental methods (SIMS, ESCA, etc.), there are a number of less-common techniques that can be valuable but require significant equipment investment, specialized operators, and administrative infrastructure to make them available to analysts, if needed. Ion beam analysis methods (RBS, PIXE, NRA), found at the Bordeaux Nuclear Research Center (France), are examples of these specialized tool sets. The capabilities and improved sensitivities of this site for device examination are demonstrated by several examples.

正电子能谱可以识别缺陷深度within metals and semiconductors with a resolution better than a single atomic lattice site. This article discusses the basic principles and implementation of positron annihilation spectroscopy and a key development that makes it more a more useful tool for semiconductor applications.

Electron beam induced current (EBIC) analysis is a versatile tool that can be used by anyone with access to a SEM. This article explains how failure analysts are using the EBIC mode in SEMs to detect junction and oxide defects, simplify junction delineation, and reveal subsurface damage through multiple layers of metallization.

Lock-in thermography (LIT) is a powerful fault isolation and characterization tool for solar cell ICs. This article describes the basic LIT imaging process on silicon wafer-based solar cells as well as its various modes, applications, and results.