Abstract
Sandia National Laboratories manufactures 0.5 µm CMOS ICs using local oxidation of silicon (LOCOS) and shallow trench isolation (STI) technologies. A program based on burn-in and life tests is being used to qualify the process for military and space applications. Representative ICs from baseline wafer lots are assembled in ceramic packages and electrically tested before, during, and after burn-in and subsequent life tests. Two types of ICs are being used for this qualification, a 256K-bit SRAM and a microcontroller core. More than 600 ICs have passed qualification tests with very few failures, although recently, a group of SRAMs from a development wafer lot incorporating nonqualified processes had an usually high number of failures during their initial electrical test after packaging. This article describes the investigation that was conducted to determine the cause of these failures.
