Nanoprobing SRAM Bit Cells with High-Speed Pulses

This article presents a nanoprobing method that uses high-speed pulses to characterize in-die SRAM bit cells. The authors describe the basic setup of the test system and demonstrate its use on a six-transistor bit cell failure. The method reduces fault localization time and decreases the possibility of deprocessing past the fail because testing is done at metallization layer 1. The bit’s reaction is captured in the form of analog current measurements, resulting in a unique signature of the failure.