How Effective Are Failure Analysis Methods for the 65 nm CMOS Technology Node?

This article assesses the capabilities of failure analysis techniques in the context of 65 nm CMOS ICs. It demonstrates the use of OBIRCH, voltage contrast, Seebeck effect imaging, SEM and TEM techniques, and FIB cross-sectioning on failures such as dielectric breakdown, open and resistive vias, voids, shorts, delaminations, and gate oxide defects.