This article discusses the causes and effects of stuck-open faults (SOFs) in nanometer CMOS ICs. It addresses detection and localization challenges and explains how resistive contacts and vias and the use of damascene-copper processes contribute to the problem. It also discusses layout techniques that reduce the likelihood of SOF failures.

damascene process, IC layout, resistive vias, stuck-open fault
This content is only available as a PDF.
Copyright © ASM International® 2006
2006
ASM International
Topics
Semiconductor wafer fabrication
You do not currently have access to this content.