Interconnect Layout Sensitivity and Yield Prediction

Layout sensitivity, a measure of vulnerability to yield loss, typically takes several days to compute for a modern VLSI design. In this article, the authors present and demonstrate a new stochastic model that can significantly expedite the process. The model is based on simple IC layout parameters including wire width, wire spacing, and channel density. The authors explain how they derived the model and how it compares to actual data. They also discuss the causes and effects of open and short defects and define the concepts of critical area and layout sensitivity.