This article presents a case study involving flash memory bit failures characterized by threshold voltage changes due to positive gate disturb stress. An inconsistency in failing bit behavior, which was found to be dependent on the test mode, was explored to provide an electrical explanation for the failure. The underlying defect was isolated and subsequently identified by physical analysis.

bit failures, fault isolation, flash memory, positive gate disturb stress, resistive connection
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2009
ASM International
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Semiconductor wafer fabrication Root cause analysis
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