Testing the Mechanical Integrity of On-Chip Interconnects

The introduction of ultralow-k dielectrics is a recent milestone in the quest for higher clock speeds and lower power consumption in ICs. One tradeoff, however, is that interconnect stacks layered with low-k materials rather than SiO₂ are more vulnerable to mechanical damage. This article presents a method that makes it possible to assess the mechanical integrity of interconnect stacks at the wafer level. The new bump-assisted BEOL stability indentation (BABSI) test uses a nanoindentation tool to apply lateral and vertical forces to solder bumps and copper pillars on the wafer surface. By applying appropriate stresses, various aspects of integrity, such as the onset of failure modes or the weakest interface in the stack, can be determined by subsequent SEM/FIB analysis. The authors describe the basic principles of the measurement technique and some of the applications in which it was used.