Abstract
The semiconductor industry continues to scale microelectronics in accordance with Moore’s Law, as the minimum feature size on integrated circuits has decreased from 800 nm in 1993 to 90 nm in 2003 to 22 nm today. In addition, manufacturing advances include 3-D packaging, with multiple dice stacked in various configurations, and 3-D integrated circuits that use through-silicon vias or through-oxide vias to connect the various dice layers. The Intelligence Advanced Research Projects Activity (IARPA) Circuit Analysis Tools (CAT) program is developing tools and techniques to ensure that the U.S. government has capabilities for circuit analysis at future technology nodes, specifically at 22 nm and beyond, and for chips assembled using advanced packaging techniques. This column describes the CAT program activities and goals.
