This article reviews recent work aimed at characterizing soft-error effects in SRAM circuits fabricated with bulk silicon FinFETs. Accelerated tests were conducted on 6T planar and FinFET-based SRAM cells by exposing them to high-energy neutrons and alpha particles. Based on test results and simulations, the authors show that soft-error rates are much lower in FinFET devices because the geometry of the fins limits charge collection.

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