Chip-level 3D integration, where chips are thinned, stacked, and vertically interconnected using TSVs and microbumps, brings as many challenges as it does improvements, particularly in the area of failure analysis. This article assesses the capabilities of various FA techniques in light of the challenges posed by 3D integration and identifies current shortcomings and future needs.

3D stacked ICs, nondestructive testing, through-silicon vias, TSV failures
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Copyright © ASM International® 2016
2016
ASM International
Topics
Electronic packaging Scanning acoustic microscopy Semiconductor wafer fabrication X-ray radiography Thermography
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